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19-1598 Rev 0; 1/00
10-Bit, 10Msps ADC
General Description
The MAX1426 10-bit, monolithic analog-to-digital converter (ADC) is capable of a 10Msps sampling rate. This device features an internal track-and-hold (T/H) amplifier for excellent dynamic performance; at the same time, it minimizes the number of external components. Low input capacitance of only 8pF minimizes input drive requirements. A wide input bandwidth (up to 150MHz) makes this device suitable for digital RF/IF downconverter applications employing undersampling techniques. The MAX1426 employs a differential pipelined architecture with a wideband T/H amplifier to maximize throughput while limiting power consumption to only 156mW. The MAX1426 generates an internal +2.5V reference that supplies three additional reference voltages (+3.25V, +2.25V, and +1.25V). These reference voltages provide a differential input range of +2V to -2V. The analog inputs are biased internally to correct the DC level, eliminating the need for external biasing on AC-coupled applications. A separate +3V digital logic supply input allows for separation of digital and analog circuitry. The output data is in two's complement format. The MAX1426 is available in the space-saving 28-pin SSOP package. For a pin-compatible version at a higher data rate, refer to the MAX1424 or MAX1425
Features
o Differential Inputs for High Common-Mode Noise Rejection o 61dB Signal-to-Noise Ratio (at fIN = 2MHz) o Internal +2.5V Reference o 150MHz Input Bandwidth o Wide 2V Input Range o Low Power Consumption: 156mW o Separate Digital Supply Input for 3V Logic Compatibility o Single +5V Operation Possible
MAX1426
Ordering Information
PART MAX1426CAI MAX1426EAI TEMP. RANGE 0C to +70C -40C to +85C PIN-PACKAGE 28 SSOP 28 SSOP
Applications
Medical Ultrasound Imaging CCD Pixel Processing IR Focal Plane Array Radar IF and Baseband Digitization Set-Top Boxes
TOP VIEW
AGND 1 AVDD 2 REFP 3 REFIN 4
Pin Configuration
28 D0 27 D1 26 D2 25 D3 24 D4
Functional Diagram
CLK INTERFACE INP T/H INN REF SYSTEM + BIAS PIPELINE ADC AVDD AGND
REFN 5 CML 6 AGND 7
MAX1426
23 DGND 22 DVDD 21 DGND 20 DVDD 19 D5 18 D6 17 D7 16 D8 15 D9
MAX1426
AVDD 8 INP 9 INN 10
OUTPUT DRIVERS
D9-D0 DVDD DGND
CMLP 11 CMLN 12 CLK 13 OE/PD 14
REF
REFIN REFP
CML REFN
OE/PD
SSOP
________________________________________________________________ Maxim Integrated Products
1
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10-Bit, 10Msps ADC MAX1426
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND ........................................................ -0.3V to +6V DVDD to DGND ....................................................... -0.3V to +6V AVDD to DGND ........................................................ -0.3V to +6V DGND to AGND ................................................................. 0.3V REFP, REFIN, REFN, CMLN, CMLP, CML, INP, INN .....................(VAGND - 0.3V) to (VAVDD + 0.3V) CLK, OE/PD, D0-D9 ...............(VDGND - 0.3V) to (VDVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 28-Pin SSOP (derated 9.5mW/C above +70C) .........762mW Operating Temperature Ranges MAX1426CAI ..................................................... 0C to +70C MAX1426EAI................................................... -40C to +85C Maximum Junction Temperature .................................... +150C Storage Temperature Range ............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = VDGND = 0, internal reference, digital output loading 35pF, fCLK = 10MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER ACCURACY Resolution Differential Nonlinearity Integral Nonlinearity No Missing Codes Midscale Offset MSO RES DNL INL Guaranteed monotonic (Note 1) Internal reference (Note 1) Gain Error GE External reference (REFIN) (Note 2) External reference (REFP, CML, REFN) (Note 3) Power-Supply Rejection Ratio Signal-to-Noise Ratio Spurious-Free Dynamic Range Total Harmonic Distortion (first five harmonics) Signal-to-Noise and Distortion PSRR SNR SFDR THD SINAD (Note 4) f = 2MHz f = 2MHz f = 2MHz f = 2MHz 58 DYNAMIC PERFORMANCE (VINP - VINN = +2V to -2V) 60 69 61 72 -70 60 -67 dB dB dB dB -3 -10 -5 -5 -5 1.0 5 2 3 2 3 10 5 5 +5 mV/V %FSR %FSR -1 -1.5 0.3 10 1 1.5 Bits LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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10-Bit, 10Msps ADC
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = VDGND = 0, internal reference, digital output loading 35pF, fCLK = 10MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Effective Number of Bits Intermodulation Distortion ANALOG INPUT (INP, INN, CML) Input Resistance Input Capacitance Input Common-Mode Voltage Range Differential Input Range Small-Signal Bandwidth Large-Signal Bandwidth Input Resistance Input Capacitance Differential Reference Input Current Input Capacitance REFP Input Range CML Input Range REFN Input Range REFERENCE OUTPUTS (REFP, CML, REFN; external +2.5V reference) Positive Reference Voltage Common-Mode Reference Voltage Negative Reference Input Voltage Differential Reference Differential Reference Temperature Coefficient VREFP VCML VREFN VREFP - VREFN, TA = +25C 1.9 3.25 2.25 1.25 2.0 50 2.1 V V V V ppm/C IIN CIN RIN CIN VCMVR DR SSBW LSBW RIN CIN Either input to ground Either input to ground CML (Note 6) VINP - VINN (Note 7) (Note 7) REFIN (Note 8) REFIN VREFP - VREFN REFP, CML, REFN REFP, CML, REFN -325 15 3.25 10% 2.25 10% 1.25 10% 6.5 10 2.0 +325 3.5 8 2.25 10% 2 400 150 k pF V V MHz MHz k pF V A pF V V V SYMBOL ENOB IMD f = 2MHz f1 = 1.98MHz, f2 = 2.00MHz (-7dB FS, each tone) (Note 5) CONDITIONS MIN 9.3 TYP 9.7 -70 MAX UNITS Bits dBc
MAX1426
REFERENCE (VREFIN = 0; REFP, REFN, CML applied externally)
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10-Bit, 10Msps ADC MAX1426
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = VDGND = 0, internal reference, digital output loading 35pF, fCLK = 10MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Positive Reference Common-Mode Reference Voltage Negative Reference Differential Reference Differential Reference Temperature Coefficient POWER SUPPLY Analog Supply Voltage Digital Supply Voltage Analog Supply Current Analog Supply Current with Internal Reference in Shutdown Analog Shutdown Current Digital Supply Current Digital Shutdown Current Power Dissipation DIGITAL INPUTS (CLK, OE/PD) VDVDD > 4.75V Input Logic High VIH VDVDD < 4.75V VDVDD > 4.75V Input Logic Low VIL VDVDD < 4.75V VDVDD = 5.25V ICLK IOE/PD -10 -20 10 VDVDD - 0.5 -10 10 2.4 0.7 x VDVDD 0.8 0.3 x VDVDD 10 20 V A A pF V PD IDVDD VAVDD VDVDD IAVDD REFIN = AGND OE/PD = DVDD VDVDD = 3.3V VDVDD = 5.0V OE/PD = DVDD 4.75 2.7 5.00 3.3 29 25 0.6 3.3 5.3 40 156 5.25 5.5 38 35 1 6 8 150 210 V V mA mA mA mA A mW SYMBOL VREFP VCML VREFN (Note 1) (Note 1) (Note 1) VREFP - VREFN, TA = +25C 1.8 CONDITIONS MIN TYP 3.25 2.25 1.25 2 150 2.2 MAX UNITS V V V V ppm/C
REFERENCE OUTPUT (REFP, CML, REFN; internal +2.5V reference)
Input Current Leakage Input Capacitance DIGITAL OUTPUTS (D0-D9) Output Logic High Output Logic Low Three-State Leakage Three-State Capacitance VOH VOL
IOH = -200A, VDVDD = 2.7V IOL = 200A, VDVDD = 2.7V VDVDD = 5.25V, OE/PD = DVDD OE/PD = DVDD
VDV
DD
V V A pF
0.5 10
4
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10-Bit, 10Msps ADC
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = VDGND = 0, internal reference, digital output loading 35pF, fCLK = 10MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER TIMING CHARACTERISTICS Conversion Rate Clock Frequency Clock High Clock Low Pipeline Delay (Latency) Aperture Delay Aperture Jitter Data Output Delay Bus Enable Bus Disable Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: tAD tAJ tOD 5 CONV fCLK tCH tCL Figure 4 Figure 4 40 40 50 50 5.5 5 7 20 10 10 25 20 20 0.1 10 10 60 60 MHz MHz ns ns cycles ns ps ns ns ns SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1426
Internal reference, REFIN bypassed to AGND with a 0.1F capacitor. External +2.5V reference applied to REFIN. Internal reference disabled. VREFIN = 0, VREFP = 3.25V, VCML = 2.25V, and VREFN = 1.25V. Measured as the ratio of the change in midscale offset voltage for a 5% change in VAVDD using the internal reference. IMD is measured with respect to either of the fundamental tones. Specifies the common-mode range of the differential input signal supplied to the MAX1426. Defined as the input frequency at which the fundamental component of the output spectrum is attenuated by 3dB. VREFIN is internally biased to +2.5V through a 5k resistor.
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10-Bit, 10Msps ADC MAX1426
Typical Operating Characteristics
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = 0, internal reference, digital output load = 35pF, fCLK = 10MHz (50% duty cycle), for dynamic performance 0dB is full scale, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. CODE
MAX1426-01
DIFFERENTIAL NONLINEARITY vs. CODE
fINP = 2MHz 0.4 0.2 DNL (LSB) 0 -0.2 -0.4 -0.6
MAX1426-02
ANALOG INPUT BANDWIDTH (FULL POWER)
-1.0 -2.0 AMPLITUDE (dB) -3.0 -4.0 -5.0 -6.0 -7.0 -8.0
MAX1426-03
0.8 0.6 0.4 0.2 INL (LSB) 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 0 200 400 CODE 600 800 fINP = 2MHz
0.6
0
1000
0
200
400 CODE
600
800
1000
0.01
0.1
1
10
100
1000 10,000
BANDWIDTH (MHz)
INTERMODULATION DISTORTION
MAX1426-04
SIGNAL-TO-NOISE PLUS DISTORTION vs. POWER (fIN = 1.997MHz)
MAX1426-05
SIGNAL-TO-NOISE RATIO PLUS DISTORTION vs. POWER (fIN = 4.942MHz)
MAX1426-06
0 -20 MAGNITUDE (dB) -40 fCLK = 10MHz f1 = 1.98MHz f2 = 2.00MHz
80
80
60 SINAD (dB) SINAD (dB) -60 -45 -30 INPUT (dB) -15 0
60
-60 -80 -100 -120 -140 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz)
40
40
20
20
0
0 -60 -45 -30 INPUT (dB) -15 0
SIGNAL-TO-NOISE RATIO vs. POWER (fIN = 1.997MHz)
MAX1426-07
SIGNAL-TO-NOISE RATIO vs. POWER (fIN = 4.942MHz)
MAX1426-08
SPURIOUS-FREE DYNAMIC RANGE vs. POWER (fIN = 1.997MHz)
70 60 SFDR (dB) 50 40 30 20 10 0
MAX1426-09
70 60 50 SNR (dB)
70 60 50 SNR (dB) 40 30 20 10 0
80
40 30 20 10 0 -60 -45 -30 INPUT (dB) -15 0
-60
-45
-30 INPUT (dB)
-15
0
-60
-45
-30 INPUT (dB)
-15
0
6
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10-Bit, 10Msps ADC
Typical Operating Characteristics (continued)
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = 0, internal reference, digital output load = 35pF, fCLK = 10MHz (50% duty cycle), for dynamic performance 0dB is full scale, TA = +25C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE vs. POWER (fIN = 9.942MHz)
MAX1426-10
MAX1426
TOTAL HARMONIC DISTORTION vs. POWER (fIN = 1.997MHz)
MAX1426-11
TOTAL HARMONIC DISTORTION vs. POWER (fIN = 4.942MHz)
MAX1426-12
80
0
0
60 SFDR (dB) THD (dB)
-20 THD (dB) -60 -45 -30 INPUT (dB) -15 0
-20
40
-40
-40
20
-60
-60
0 -60 -45 -30 INPUT (dB) -15 0
-80
-80 -60 -45 -30 INPUT (dB) -15 0
EFFECTIVE NUMBER OF BITS vs. POWER (fIN = 1.997MHz)
MAX1426-13
EFFECTIVE NUMBER OF BITS vs. POWER (fIN = 4.942MHz)
MAX1426-14
EFFECTIVE NUMBER OF BITS vs. INPUT FREQUENCY
MAX1426-15
10
10
10.0
8
8
9.6
ENOB (bits)
ENOB (bits) -60 -45 -30 INPUT (dB) 15 0
6
ENOB (bits)
6
9.2
4
4
8.8
2
2
8.4
0 -60 -45 -30 INPUT (dB) 15 0
0
8.0 2 3 4 5 INPUT FREQUENCY (MHz)
SIGNAL-TO-NOISE RATIO vs. INPUT FREQUENCY
MAX1426-16
TOTAL HARMONIC DISTORTION vs. INPUT FREQUENCY
MAX1426-17
SIGNAL-TO-NOISE PLUS DISTORTION vs. INPUT FREQUENCY
MAX1426-18
60
-70
61
-71 59 SNR (dB) THD (dB) -72 SINAD (dB) 2 3 4 5
60
59
-73 58 -74
58
57 2 3 4 5 INPUT FREQUENCY (MHz)
-75 INPUT FREQUENCY (MHz)
57 2 3 4 5 INPUT FREQUENCY (MHz)
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10-Bit, 10Msps ADC MAX1426
Typical Operating Characteristics (continued)
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = 0, internal reference, digital output load = 35pF, fCLK = 10MHz (50% duty cycle), for dynamic performance 0dB is full scale, TA = +25C, unless otherwise noted.)
FFT PLOT (fIN = 2MHz)
MAX1426-19
FFT PLOT (fIN = 5MHz)
MAX1426-20
0 -20 MAGNITUDE (dB) -40 -60 -80 -100 -120 -140 0
0 -20 MAGNITUDE (dB) -40 -60 -80 -100 -120 -140
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz)
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (MHz)
TOTAL SUPPLY CURRENT vs. TEMPERATURE
44
MAX1426-21
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
MAX1426-22
0.85
2.18
SHUTDOWN CURRENT (mA)
REFIN = AGND 36 OE/PD = L SHUTDOWN 32 0.70 0.75
INTERNAL REFERENCE (V)
40 SUPPLY CURRENT (mA)
0.80
2.16
2.14
2.12
28
REFIN = GND
0.65
2.10
24 -40 -15 10 35 60 85 TEMPERATURE (C)
0.60
2.08 -40 -15 10 35 60 85 TEMPERATURE (C)
8
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10-Bit, 10Msps ADC
Pin Description
PIN 1, 7 2, 8 3 NAME AGND AVDD REFP FUNCTION Analog Ground. Connect all return paths for analog signals to these pins. Analog Supply Voltage Input. Bypass with a parallel combination of 2.2F, 0.1F, and 100pF capacitors to AGND. Bypass each supply input to the closest AGND (e.g., capacitors between pins 1 and 2). Positive Reference Output. Bypass to AGND with a 0.1F capacitor. If the internal reference is disabled, REFP can accept an external voltage. External Reference Input. Bypass to AGND with a 0.1F capacitor. REFIN can be biased externally to adjust the reference level and calibrate full-scale errors. To disable the internal reference, connect REFIN to AGND. Negative Reference Output. Bypass to AGND with 0.1F capacitor. REFN can accept an external voltage when the internal reference is disabled (REFN = AGND). Common-Mode Level Input. Bypass to AGND with a 0.1F capacitor. CML can accept an external voltage when the internal reference is disabled (REFN = AGND). Positive Analog Signal Input Negative Analog Signal Input Common-Mode Level Positive Input. For AC applications, connect to AVDD to internally set the input DC bias level. For DC-coupled applications, connect to AGND. Common-Mode Level Negative Input. Connect to AGND to internally set the input DC bias level for both AC- and DC-coupled applications. Clock Input. Clock frequency range from 0.1MHz to 10MHz. Active-Low Output Enable and Power-Down Input. Digital outputs become high impedance and device enters low-power mode when pin is high. Digital Data Output (MSB) Digital Data Outputs 8-5 Digital Supply Voltage Input. Bypass with 2.2F and 0.1F capacitors in parallel. Digital supply can operate with voltages as low as +2.7V. Digital Ground Digital Data Outputs 4-1 Digital Data Output (LSB)
MAX1426
4
REFIN
5 6 9 10 11 12 13 14 15 16-19 20, 22 21, 23 24-27 28
REFN CML INP INN CMLP CMLN CLK OE/PD D9 D8-D5 DVDD DGND D4-D1 D0
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10-Bit, 10Msps ADC MAX1426
Detailed Description
The MAX1426 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for high-speed conversion while minimizing power consumption. Each sample moves through a pipeline stage every half clock cycle. Counting the delay through the output latch, there is a 5.5 clock-cycle latency. A 2-bit flash ADC converts the input voltage to digital code. A DAC converts the ADC result back into an analog voltage, which is subtracted from the held input signal. The resulting error signal is then multiplied by two, and this product is passed along to the next pipeline stage where the process is repeated. Digital error correction compensates for offsets and mismatches in each pipeline stage and ensures no missing codes. the residue by two and the next stage in the pipeline performs a similar operation.
System Timing Requirements
Figure 3 shows the relationship between the clock input, analog input, and data output. The MAX1426 samples the falling edge of the input clock. Output data is valid on the rising edge of the input clock. The output data has an internal latency of 5.5 clock cycles, as shown. Figure 4 shows an output timing diagram that specifies the relationship between the input clock parameters and the valid output data.
Analog Input and Internal Reference
The MAX1426 has an internal +2.5V reference used to generate three reference levels: +3.25V, +2.25V, and +1.25V corresponding to V REFP, V CML, and V REFN. These reference voltages enable a 2V input range. Bypass all reference voltages with a 0.1F capacitor. The MAX1426 allows for three modes of reference operation: an internal reference (default) mode, an externally adjusted reference mode, or a full external reference mode. The internal reference mode occurs when no voltages are applied to REFIN, REFP, CML,
CML S3a INP REFP S4a S4c C2b S4b C1b S2b CML a) TRACK MODE CML S3a INP C1a S2a C2a S1 C1a S2a
Internal Track-and-Hold Circuit
Figure 2 shows a simplified functional diagram of the internal track-and-hold (T/H) circuit in both track mode and hold mode. The fully differential circuit samples the input signal onto the four capacitors C1a, C1b, C2a, and C2b. Switches S2a and S2b set the common mode for the amplifier input, and open before S1. When S1 opens, the input is sampled. Switches S3a and S3b then connect capacitors C1a and C1b to the output of the amplifier. Capacitors C2a and C2b are connected either to REFN, REFP, or each other, depending on the results of the flash ADC. The amplifier then multiplies
MDAC VIN T/H x2 VOUT
REFN REFP REFN INN
FLASH ADC 2 BITS
DAC
VIN
S4a
C2a S4c C2b S1
STAGE 1
STAGE 2
STAGE 10
REFP REFN REFP REFN INN
S4b S3b C1b S2b CML
DIGITAL CORRECTION LOGIC 10 D [9:0]
b) HOLD MODE
Figure 1. Pipelined A/D Architecture (Block) 10
Figure 2. Internal Track-and-Hold Circuit
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10-Bit, 10Msps ADC MAX1426
5.5 CLOCK-CYCLE LATENCY n n+1 n+2 n+3 n+4 n+5 n+6 n+7
ANALOG INPUT
CLOCK INPUT
DATA OUTPUT
n-6
n-5
n-4
n-3
n-2
n-1
n
n+1
Figure 3. System Timing Diagram
Table 1. MAX1426 Output Code
tCLK tCH INPUT CLK tOD tCI
DIFFERENTIAL INPUT +Full Scale +Full Scale 1LSB +Full Scale 2LSB +3/4 Full Scale
OUTPUT CODE (TWO'S COMPLEMENT) 0111111111 0111111110 0111111101 0110000000 0100000000 0010000000 0000000001 0000000000 1111111111 1110000000 1100000000 1010000000 1000000001 1000000000
OUTPUT DATA
DATA 0
DATA 1
DATA 2
+1/2 Full Scale +1/4 Full Scale
Figure 4. Output Timing Diagram
+1 LSB Bipolar Zero
and REFN. In this mode, the voltages at these pins are set to their nominal values (see Electrical Characteristics). The reference voltage levels can be adjusted externally by applying a voltage at REFIN. This allows other input levels to be used as well. The full external reference mode is entered when REFIN = AGND. External voltages can be applied to REFP, CML, and REFIN. In this mode, the internal voltage shuts down, resulting in less overall power consumption.
-1 LSB -1/4 Full Scale -1/2 Full Scale -3/4 Full Scale -Full Scale + 1LSB -Full Scale
Clock Input (CLK)
CLK is TTL/CMOS compatible. Since the interstage conversion of the device depends on the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). Low clock jitter improves SNR performance. The MAX1426 operates with a 50% duty cycle. If the clock has a duty cycle other than 50%, the clock must meet the specifications for high and low periods as stated in the Electrical Characteristics.
Output Enable/Power-Down Function (OE/PD) and Output Data
All data outputs, D0 through D9, are TTL/CMOS-logic compatible. There is a 5.5 clock-cycle latency between the start convert signal and the valid output data. The output coding for the MAX1426 is in binary two's complement format, which has the MSB inverted (Table 1). The digital output goes into a high-impedance state and the device into a low-power mode when OE/PD goes high. For normal operation, drive OE low. The outputs are not designed to drive high capacitances or
11
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10-Bit, 10Msps ADC MAX1426
heavy loads, as they are specified to deliver only 200A for TTL compatibility. If an application needs output buffering, use 74LS74s or 74ALS541s as required. high-speed op amps. In this application, the amplifier outputs are directly coupled to the inputs. This configuration can also be modified for AC-coupled applications. The MAX1426 includes a DC level-shifting circuit internal to the part, allowing for AC-coupled applications. The level-shifting circuit is shown in Figure 6. The circuit in Figure 6 can accept a 1Vp-p maximum input voltage. With a maximum clock frequency of 10MHz, use 50 termination to minimize reflections. Buffer the digital outputs with a low-cost, high-speed,
Applications Information
Figure 5 shows a typical application circuit containing a single-ended to differential converter. The internal reference provides a +2.25V output for level shifting. The input is buffered and then split to a voltage follower and inverter. The op amps are followed by a lowpass filter to remove some of the wideband noise associated with
+5V
0.1F BAS16 MAX4108 300 0.1F 0.1F -5V 0.1F
300
INP 50 22pF
MAX1426
600 CML +5V 2.5k 0.1F 300 600 MAX473A
0.1F
0.1F +5V 2.5k +5V 0.1F INPUT 0.1F MAX4108 300 50 -5V 0.1F 300 -5V 25 25 600 0.1F MAX4108 BAS16 22pF 600 300 0.1F 50 INN 50
Figure 5. Typical Application Circuit Using the Internal Reference 12 ______________________________________________________________________________________
10-Bit, 10Msps ADC
octal D-latched flip-flop (74ALS374), or use octal buffers such as the 74ALS541.
Using Transformer Coupling
A small transformer (Figure 8) provides isolation and AC-coupling to the ADC's input. Connecting the transformer's center tap to CML provides a +2.25VDC level shift to the input. Transformer coupling reduces the need for high-speed op amps, thereby reducing cost. Although a 1:1 transformer is shown, a step-up transformer may be selected to reduce the drive requirements.
MAX1426
Typical Application Using an External Reference
Figure 7 shows an application circuit that shuts down the internal reference, allowing an external reference to be used for selecting a different common-mode voltage. This added flexibility also allows for ratiometric conversions, as well as for calibration.
Single-Ended DC-Coupled Input Signal
CMLP
Figure 9 shows an AC-coupled, single-ended application. The MAX4106 quad op amp provides high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal.
5.5k 5.5k
INP TO T/H INPUT INN
4.5k
4.5k
CMLN
Figure 6. Analog Input DC Bias Circuit
VDD 50 R 0.1F VDD 2 R
MAX4284 MAX4284
CML
DD (V2 )
50 REFP 0.1F VDD 2 VDD 4
MAX4284 DD ( V2 + 1V )
R
R
MAX1426
R 50 REFN 0.1F VDD 4 R REFIN R AGND
DD ( V2 - 1V )
R
+1V
Figure 7. Using an External Reference for REFP, REFN, and CML (internal reference shut down) ______________________________________________________________________________________ 13
10-Bit, 10Msps ADC MAX1426
R4 25 INN C3 22pF MAX1426 IN1 1 N.C. 2 R2 100 R3 100 3 T1 6 5 4 0.1F R5 25 INP C9 22pF
VIN V 50 MAX4108
2V 0.1F 50 INP 22pF 100
MAX1426
100 0.1F
CML
INN
MINICIRCUITS KKB1
Figure 9. Single-Ended AC-Coupled Input Signal
Figure 8. Using a Transformer for AC-Coupling
Bypassing and Board Layout
The MAX1426 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, using surface-mount devices for minimum inductance. Bypass all analog voltages (AV DD , REFIN, REFP, REFN, and CML) to AGND. Bypass the digital supply (DVDD) to DGND. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Route highspeed digital signal traces away from sensitive analog traces. Matching impedance, especially for the input clock generator, may reduce reflections, thus providing less jitter in the system. For optimum results, use lowdistortion complementary components such as the MAX4108.
Chip Information
TRANSISTOR COUNT: 5305
14
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10-Bit, 10Msps ADC
________________________________________________________Package Information
SSOP.EPS
MAX1426
______________________________________________________________________________________
15
10-Bit, 10Msps ADC MAX1426
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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